As devices become smaller and integration density increases, reactive ion etching (RIE) has become a key process in anisotropic etching of semiconductor features. RIE or ion-enhanced etching works by a combination of physical and chemical mechanisms for achieving etch selectivity and anisotropy. In some applications, for example, etching high aspect ratio features such as vias, high density plasma (HDP) etching has been increasingly used in etching high aspect ratio features, for example, with aspect ratios greater than about 3:1.
During the formation of semiconductor devices it is often required that the conductive layers be interconnected through high-aspect-ratio holes in inter-metal dielectric (IMD) layers. Such holes are commonly referred to as contact holes, i.e., when the hole extends through an insulating layer to an active device area, or vias, i.e., when the hole extends through an insulating layer between two conductive layers. The profile of a hole is of particular importance since it exhibits specific electrical characteristics when the contact hole or via is filled with a conductive material. Typically, the holes are high aspect ratio holes, meaning that the ratio of length to width is greater than about 3. Such holes are typically formed by a reactive ion etching (RIE) process where complex chemical processes assisted by ion bombardment result in relatively higher etching rates in one direction versus another, known as anisotropic etching. The relative anisotropy or selectivity of the etching process will in turn determine the etching profile of an etched hole and consequently its aspect ratio. As semiconductor structures are inevitably driven to smaller sizes, successful etching of higher aspect ratio holes is becoming more difficult.
A common phenomenon in multi-level semiconductor devices is charge accumulation during plasma processing. For example, charged species may become incorporated within the surface of the layer, with localized charge accumulation aided by defects formed in the dielectric insulating layer. As dielectric insulating layers have decreased in dielectric constant, their increased electrical insulating characteristics also contribute to the localized buildup of electrical charge within the insulating portion of the multi-level device. The electrical charge build-up is frequently long lasting, lasting at least for several hours.
One detrimental effect of the localized accumulation of charge in the dielectric insulating layer is arcing. The problem of arcing or electrical discharge of the plasma to localized charged areas on the semiconductor wafer has increasingly become a critical problem in RIE processes. The arcing damage typically occurs near a metallization line, which is believed to provide a pathway to localized charged areas in the dielectric layer. The problem is critical since the damage caused by the arcing typically is typically severe and the extent of damage to underlying regions and surrounding areas not readily ascertainable making further processing of the wafer impractical. As a result, arcing damage to the wafer is costly in terms of wafer yield and reliability.
One semiconductor area where plasma arcing is a problem is in the fabrication of programmable stackable memory arrays. Shown in FIG. 1 is a conventional intermediate stackable field programmable EPROM comprising a plurality of vertical p-i-n polysilicon antifuse diodes. In a first level of memory cells, are a plurality of conventional memory cell diodes 108, the diodes having a thin SiO2 or nitride antifuse layer (not shown). The memory cell diodes 108 are connected to a plurality of bitlines 111, the bitlines 111 being interposed between a TiN barrier layer 109 and a suitable underlying layer 102. The opposite end of the memory cell diodes are connected to a tungsten wordline 117, with another TiN barrier layer 118 interposed between. Conventional stacked EPROMs further include a dielectric layer 120 on the wordline 117, a first conductor 114, and a second conductor 127. On the dielectric layer 120 is a second plurality of memory cell diodes 121 having another TiN barrier layer 122 and bitlines 123, essentially the same as that of the first memory cell layer.
After forming the EPROM structure described above, a typical fabrication sequence includes depositing a fourth TiN barrier layer 133. It is typically after depositing barrier layer 133 that deep via plasma etching occurs.
Turning now to FIG. 2, there is illustrated a plasma etched via 134 formed down to a suitable conductor 105 within the underlying layer 102. As shown in FIG. 2, plasma etching of via 134 involves simultaneously exposing TiN layer 136 and tungsten wordline layer 117 to the plasma. At this stage of a conventional fabrication process, TiN layer 136 and tungsten wordline layer 117 are floating conductors. Therefore, during plasma forming of via 134, a charge imbalance may occur between TiN layer 136 and wordline layer 117 thereby causing these to layers to become essentially a charged capacitor. As described above, arcing may occur. Referring to FIG. 2, arcing may occur between TiN layer 136 and an exposed corner of wordline layer 139 thereby damaging surrounding structures.
In light of these and other problems, there is a need for a method that avoids plasma arcing during plasma processing of dielectric layers.